Binghamton University EECE
Gate level and physical level design of a complex system, such as RISC processor (including the ALU and memory) is discussed. Advanced topics in logic-level design, such as high performance design, dynamic logic, low power design, asynchronous logic, interconnect analysis, cross talk issues, bus architecture, layout floor planning, and placement and routing, will be covered. Students will be asked to use Cadence physical design, analysis, and simulation tools. Prerequisite: EECE 574. Offered every spring semester.
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